As integrated circuit, there is generally a piece of silicon known as a die or chip which contains electrical circuit and which is connected to a lead frame. The chip has bonding pads which connected to the lead frame by tiny wires. The lead frame has leads which are used for connecting to a printed circuit board as part of a larger system. The leads of the lead frame have a certain amount of inductance as well ad capacitance and resistance. There is also some inductance in the wire from the bonding pad to the lead frame. The wire inductance, however, is significantly less than that of the lead frame. The connection of a lead of the lead frame to a circuit board also adds some inductance. As the switching speeds of integrated circuits have increased, this cumulative inductance has begun to have an impact on the performance of the integrated circuit.
Of course it is desirable to have integrated circuits which are very fast. The increased switching speed has also increased the rate at which current changes. This increased rate of current change causes a voltage drop across the inductance. The voltage across an inductance is equal to the inductance times the time rate of change of the current through that inductance. This is expressed as Ldi/dt, where L is the inductance and di/dt is the time rate of change of the current. As the di/dt becomes larger, the voltage across the inductance becomes larger. This voltage drop across an inductance causes a voltage differential between the lead location on the circuit board and the bonding pad to which it is connected on the integrated circuit. This can create a problem of having an internal supply at a different voltage than the voltage of a corresponding external supply. This problem can cause the internal supply voltages to differ by so much from their external levels that signals input to the chip are recognized incorrectly.
Conventional method of reducing di/dt focus on output buffers themselves. (See Wang, Karl L., et. al, "A 21-ns 32K.chi.8 CMOS Static RAM with a selectively Pumped p-Well Array, " IEE Journal of Solid-State Circuits, vol. SC-22, no. 5, October 1987; Wang, et al. in a U.S. patent application Ser. No. 07/348357 entitled "A Low di/dt Output Buffer with Improved Speed". ) In integrated circuit memories, there is a tradeoff between access time and di/dt. As access times are force down, new approaches must be found to reduce di/dt for a given access time.